This invention relates to the manufacture of multilayer semiconductor circuit devices, in which the growth of field oxide regions serves to isolate devices on a circuit array.
The invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". One of the materials used is silicon, which appears as either single crystal silicon or as polycrystalline silicon material, referred to as polysilicon or "poly" in this disclosure.
While silicon is used in the preferred embodiment, as is known to those skilled in the art of semiconductor manufacture, the invention is applicable to other doped semiconductor material.
An electronic circuit is chemically and physically integrated into a substrate such as a silicon wafer by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication. They can also be of differing conductivity types, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, or conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible.
In this disclosure, "n" denotes silicon that has been doped with atoms having more than four valence electrons (group V or higher), such as arsenic or phosphorus, which introduce negatively charged majority carriers into the silicon, and "p" denotes silicon doped with atoms having less than four valence electrons (group III or lower), such as boron, which introduce positively charged majority carriers. The majority charge carrier type is also referred to as conductivity type. A plus or minus superscript on an n or p indicates heavy or light doping, respectively. "Poly" denotes polycrystalline silicon.
A process known as LOCal Oxidation of Silicon (LOCOS) has become the standard device isolation technique, due to the semi-recessed topography of the field oxide, low defect density, and the self-aligning nature of the field implant, particularly in n-channel field regions. With conventional LOCOS technology, array area is wasted in oxide transition regions known as the "bird's beak" regions. A very gradual slope of the bird's beak region not only wastes space, but also hampers subsequent fine-line lithography operations which, for VLSI devices, is best suited to planar surface topography.
One of the more basic improvements to LOCOS which results in somewhat more planar surface topography and a reduction in the size of the bird's beak region is the etchback process. The effectiveness of this technique is limited by two factors--an increase in the effective size of the field implant encroachment region and the degree of remaining surface nonplanarity following the etchback.
One key factor in maximizing the active area is reducing field oxide encroachment into active area during field oxidation. Encroachment can case a loss of active width up to twice the field ox thickness. As geometries shrink in more advanced generation DRAMs, this effect becomes a dominant factor. A common method of approaching this problem involves use of some sort of field oxidation encroachment reduction technique. Several techniques are discussed in the literature including SWAMI, SILO, BOX, Poly Buffer, Nitrox, trench isolation, and others. Each has their advantages and disadvantages, but all involve adding a great deal of added complexity to the process.
The cause of field oxide bird's beak effect (bird's beak) initiates from process steps used to isolate an active area location of a storage cell. The Local Oxidation Of Silicon (LOCOS) process, a method commonly used to isolate active areas in a memory array during the production of a semiconductor device (LSI, VLSI, etc.), constitutes the use of thick field oxide.
Initially, the silicon wafer is prepared using conventional process steps such as those used for defining and forming CMOS wells. This is followed by growing a thin layer of pad oxide, usually silicon dioxide, over the wafer surface. Next, a layer of nitride is deposited on the wafer which is then patterned and etched away from all areas except those defined as active areas. Field oxide is then grown over the areas that were not previously covered with nitride and as it grows it begins to encroach under the edge of the nitride layer.
This oxide encroachment under the nitride, known as bird's beak, results in the actual area of the active areas being reduced after field oxidation is complete. Therefore, reducing bird's beak becomes a critical factor in maximizing the cell's active areas.
As geometries shrink in more advanced generation DRAMs, bird's beak becomes a dominant limiting factor to the number of cells that can effectively be packed into a given die.
The outer limits of the LOCOS process is the result of field oxide thinning in narrow field regions that results from a poor oxidant supply in these narrow regions. This invention has, as one of its objects, the reduction of this thinning effect.
The thinning effect is the result of the close proximity of two nitride sidewalls. Experience shows that a field width of 4000 .ANG. will be subject to this thinning effect, although significant thinning may occur on field areas wider than that. The actual cause of the field oxide thinning is not clear, though.
One possibility is that, as a result of the narrow dimension, there is a reduced supply of oxidant species available for field oxide growth. A second possible factor is that, because of the narrow width, a different stress occurs on the oxidizing Si in the narrow regions, as a sort of reverse birds beak effect.
A third possibility is that the oxidation requires mobile oxygen molecules to enter the oxide forming over the Si at a preferred angle of incidence in order to more readily enter the silicon dioxide lattice structure. If the narrow width, such as the 4000 .ANG. in the example, is sufficiently narrow to inhibit the free movement of the oxygen molecules in the preferred direction, then the degree of oxidation would be correspondingly reduced.
As chip density increases, each layer or component is designed to be smaller and thinner. This is particularly the case of the field oxide used to isolate adjacent devices. If a standard LOCOS process is used, the bird's beak length approaches the critical device dimensions, and a large area on the chip is lost due to these bird's beak transition regions. Thus, there is a need to build field oxide structures with reduced bird's beaks.
In order to produce narrow field regions and reduce bird's beak effect, a poly buffer LOCOS process was developed. In the poly buffer LOCOS process (PBL), a pad oxide layer is grown, followed by a poly layer and by a nitride layer. The poly layer is placed to absorb the stress created by the nitride film. This is followed by the patterning of the nitride with photoresist in order to define active areas and field regions. The nitride is etched away through the photoresist, after which the resist was striped. This leaves areas of nitride which were defined by the photoresist. Field oxide is grown on parts of the area not covered by nitride, so that the areas of nitride as defined by the photoresist are used to define the active areas.
The nitride pattern is stripped after the growth of the field oxide, along with the underlying buffer poly. The growth of field oxide consumes the buffer poly in the field areas of exposed regions, so the stripping of the nitride and underlying buffer poly has eliminated the buffer poly.
The PBL process permits the use of a thicker nitride layer since the buffer poly absorbs the additional stress. The increased thickness of the nitride also may result in a thinning of those field areas having a narrow width dimension. One effect of doping silicon is that the doped material is more readily oxidized.